module alu_64bit(
	input [63:0] x1,x2
	input [4:0] alu_op
	output [63:0] y
	output carry,overflow,sign,zero
)
always@*
begin
	case (alu_op):
		4'h0: begin
			y = x1 + x2;
			overflow=((x1[63]==x2[63])&&(y[63]==~x1[63]))?1:0;
		end
		4'h1: begin
			y = x1 - x2;
			overflow=((x1[63]==x2[63])&&(y[63]==x1[63]))?1:0;
		end
		4'h2: begin
		end
		4'h3: begin
		end
	endcase
end
endmodule